51 lines
2.1 KiB
Plaintext
51 lines
2.1 KiB
Plaintext
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# Copyright (C) 2023 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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# Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
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# File: /home/lambda/Programs/intelQuartus/projects/vga/vga_io.csv
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# Generated on: Sat Aug 26 14:20:03 2023
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# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
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To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
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B[7],Output,PIN_D12,8,B8_N0,PIN_AD1,,,,,,
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B[6],Output,,,,PIN_AD2,,,,,,
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B[5],Output,,,,PIN_B7,,,,,,
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B[4],Output,,,,PIN_AC2,,,,,,
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B[3],Output,,,,PIN_T8,,,,,,
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B[2],Output,,,,PIN_U6,,,,,,
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B[1],Output,,,,PIN_AD3,,,,,,
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B[0],Output,,,,PIN_R3,,,,,,
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G[7],Output,,,,PIN_AA3,,,,,,
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G[6],Output,,,,PIN_D10,,,,,,
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G[5],Output,,,,PIN_U4,,,,,,
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G[4],Output,,,,PIN_U5,,,,,,
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G[3],Output,,,,PIN_AC1,,,,,,
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G[2],Output,,,,PIN_Y4,,,,,,
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G[1],Output,,,,PIN_AB1,,,,,,
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G[0],Output,,,,PIN_R6,,,,,,
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HS,Output,,,,PIN_R5,,,,,,
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px_clk,Input,,,,PIN_J1,,,,,,
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R[7],Output,,,,PIN_Y3,,,,,,
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R[6],Output,,,,PIN_U3,,,,,,
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R[5],Output,,,,PIN_AC3,,,,,,
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R[4],Output,,,,PIN_G23,,,,,,
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R[3],Output,,,,PIN_AA4,,,,,,
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R[2],Output,,,,PIN_AB2,,,,,,
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R[1],Output,,,,PIN_W1,,,,,,
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R[0],Output,,,,PIN_AB3,,,,,,
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rst,Input,,,,PIN_Y2,,,,,,
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VS,Output,,,,PIN_T3,,,,,,
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