library IEEE;
use IEEE.std_logic_1164.all;

entity MAIN is

  port (
    VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic;
    clk, rst                     : in  std_logic;
    R, G, B                      : out std_logic_vector (7 downto 0);
    HS, VS                       : out std_logic);

end entity MAIN;


architecture mymain of MAIN is
  component VGA is
    port(
      px_clk, rst : in  std_logic;
      R, G, B     : out std_logic_vector (7 downto 0);
      HS, VS      : out std_logic);
  end component VGA;

  component PLL is
    port (
      inclk0 : in  std_logic := '0';
      c0     : out std_logic
      );
  end component PLL;

  signal px_clk : std_logic;

begin

  --  USED BY the ADC
  VGA_BLANK <= '1';
  VGA_SYNC  <= '0';
  VGA_CLK   <= px_clk;

  myVGA : VGA port map (
    px_clk => px_clk,                   -- this signals a new px
    rst    => rst,
    R      => R,
    G      => G,
    B      => B,
    HS     => HS,
    VS     => VS);                      -- this signals a new frame

  myPLL : PLL port map (
    inclk0 => clk,
    c0     => px_clk);

end architecture;