# -------------------------------------------------------------------------- #
#
# Copyright (C) 2023  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
# Date created = 13:50:20  August 26, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		vga_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY main
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:50:20  AUGUST 26, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_location_assignment PIN_D12 -to B[7]
set_location_assignment PIN_D11 -to B[6]
set_location_assignment PIN_C12 -to B[5]
set_location_assignment PIN_A11 -to B[4]
set_location_assignment PIN_B11 -to B[3]
set_location_assignment PIN_C11 -to B[2]
set_location_assignment PIN_A10 -to B[1]
set_location_assignment PIN_B10 -to B[0]
set_location_assignment PIN_C9 -to G[7]
set_location_assignment PIN_F10 -to G[6]
set_location_assignment PIN_B8 -to G[5]
set_location_assignment PIN_C8 -to G[4]
set_location_assignment PIN_H12 -to G[3]
set_location_assignment PIN_F8 -to G[2]
set_location_assignment PIN_G11 -to G[1]
set_location_assignment PIN_G8 -to G[0]
set_location_assignment PIN_H10 -to R[7]
set_location_assignment PIN_H8 -to R[6]
set_location_assignment PIN_J12 -to R[5]
set_location_assignment PIN_G10 -to R[4]
set_location_assignment PIN_F12 -to R[3]
set_location_assignment PIN_D10 -to R[2]
set_location_assignment PIN_E11 -to R[1]
set_location_assignment PIN_E12 -to R[0]
set_location_assignment PIN_C13 -to VS
set_location_assignment PIN_G13 -to HS
set_location_assignment PIN_R24 -to rst
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name VHDL_FILE src/main.vhd
set_global_assignment -name VHDL_FILE src/vga.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_F11 -to VGA_BLANK
set_location_assignment PIN_C10 -to VGA_SYNC
set_global_assignment -name QIP_FILE pll.qip
set_location_assignment PIN_AG14 -to clk
set_location_assignment PIN_A12 -to VGA_CLK
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top