53 lines
1.1 KiB
VHDL
53 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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entity MAIN is
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port (
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VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic;
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clk, rst : in std_logic;
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R, G, B : out std_logic_vector (7 downto 0);
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HS, VS : out std_logic);
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end entity MAIN;
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architecture mymain of MAIN is
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component VGA is
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port(
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px_clk, rst : in std_logic;
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R, G, B : out std_logic_vector (7 downto 0);
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HS, VS : out std_logic);
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end component VGA;
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component PLL is
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port (
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inclk0 : in std_logic := '0';
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c0 : out std_logic
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);
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end component PLL;
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signal px_clk : std_logic;
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begin
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-- USED BY the ADC
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VGA_BLANK <= '1';
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VGA_SYNC <= '0';
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VGA_CLK <= px_clk;
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myVGA : VGA port map (
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px_clk => px_clk, -- this signals a new px
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rst => rst,
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R => R,
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G => G,
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B => B,
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HS => HS,
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VS => VS); -- this signals a new frame
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myPLL : PLL port map (
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inclk0 => clk,
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c0 => px_clk);
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end architecture;
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