51 lines
2.4 KiB
Plaintext
51 lines
2.4 KiB
Plaintext
|
# Copyright (C) 2023 Intel Corporation. All rights reserved.
|
||
|
|
# Your use of Intel Corporation's design tools, logic functions
|
||
|
|
# and other software and tools, and any partner logic
|
||
|
|
# functions, and any output files from any of the foregoing
|
||
|
|
# (including device programming or simulation files), and any
|
||
|
|
# associated documentation or information are expressly subject
|
||
|
|
# to the terms and conditions of the Intel Program License
|
||
|
|
# Subscription Agreement, the Intel Quartus Prime License Agreement,
|
||
|
|
# the Intel FPGA IP License Agreement, or other applicable license
|
||
|
|
# agreement, including, without limitation, that your use is for
|
||
|
|
# the sole purpose of programming logic devices manufactured by
|
||
|
|
# Intel and sold by Intel or its authorized distributors. Please
|
||
|
|
# refer to the applicable agreement for further details, at
|
||
|
|
# https://fpgasoftware.intel.com/eula.
|
||
|
|
|
||
|
|
# Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
|
||
|
|
# File: /home/lambda/Programs/intelQuartus/projects/vga/vga_io.csv
|
||
|
|
# Generated on: Sat Aug 26 14:34:23 2023
|
||
|
|
|
||
|
|
# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
|
||
|
|
|
||
|
|
To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
|
||
|
|
B[7],Output,PIN_D12,8,B8_N0,PIN_AD1,,,,,,
|
||
|
|
B[6],Output,PIN_D11,8,B8_N1,PIN_AD2,,,,,,
|
||
|
|
B[5],Output,PIN_C12,8,B8_N0,PIN_B7,,,,,,
|
||
|
|
B[4],Output,PIN_A11,8,B8_N0,PIN_AC2,,,,,,
|
||
|
|
B[3],Output,PIN_B11,8,B8_N0,PIN_T8,,,,,,
|
||
|
|
B[2],Output,PIN_C11,8,B8_N1,PIN_U6,,,,,,
|
||
|
|
B[1],Output,PIN_A10,8,B8_N0,PIN_AD3,,,,,,
|
||
|
|
B[0],Output,PIN_B10,8,B8_N0,PIN_R3,,,,,,
|
||
|
|
G[7],Output,PIN_C9,8,B8_N1,PIN_AA3,,,,,,
|
||
|
|
G[6],Output,PIN_F10,8,B8_N1,PIN_D10,,,,,,
|
||
|
|
G[5],Output,PIN_B8,8,B8_N1,PIN_U4,,,,,,
|
||
|
|
G[4],Output,PIN_C8,8,B8_N1,PIN_U5,,,,,,
|
||
|
|
G[3],Output,PIN_H12,8,B8_N1,PIN_AC1,,,,,,
|
||
|
|
G[2],Output,PIN_F8,8,B8_N2,PIN_Y4,,,,,,
|
||
|
|
G[1],Output,PIN_G11,8,B8_N1,PIN_AB1,,,,,,
|
||
|
|
G[0],Output,PIN_G8,8,B8_N2,PIN_R6,,,,,,
|
||
|
|
HS,Output,PIN_G13,8,B8_N0,PIN_R5,,,,,,
|
||
|
|
px_clk,Input,,,,PIN_J1,,,,,,
|
||
|
|
R[7],Output,PIN_H10,8,B8_N1,PIN_Y3,,,,,,
|
||
|
|
R[6],Output,PIN_H8,8,B8_N2,PIN_U3,,,,,,
|
||
|
|
R[5],Output,PIN_J12,8,B8_N0,PIN_AC3,,,,,,
|
||
|
|
R[4],Output,PIN_G10,8,B8_N1,PIN_G23,,,,,,
|
||
|
|
R[3],Output,PIN_F12,8,B8_N1,PIN_AA4,,,,,,
|
||
|
|
R[2],Output,PIN_D10,8,B8_N1,PIN_AB2,,,,,,
|
||
|
|
R[1],Output,PIN_E11,8,B8_N1,PIN_W1,,,,,,
|
||
|
|
R[0],Output,PIN_E12,8,B8_N1,PIN_AB3,,,,,,
|
||
|
|
rst,Input,,,,PIN_Y2,,,,,,
|
||
|
|
VS,Output,PIN_C13,8,B8_N0,PIN_T3,,,,,,
|