2.4 KiB
2.4 KiB
| 1 | # Copyright (C) 2023 Intel Corporation. All rights reserved. |
|---|---|
| 2 | # Your use of Intel Corporation's design tools, logic functions |
| 3 | # and other software and tools, and any partner logic |
| 4 | # functions, and any output files from any of the foregoing |
| 5 | # (including device programming or simulation files), and any |
| 6 | # associated documentation or information are expressly subject |
| 7 | # to the terms and conditions of the Intel Program License |
| 8 | # Subscription Agreement, the Intel Quartus Prime License Agreement, |
| 9 | # the Intel FPGA IP License Agreement, or other applicable license |
| 10 | # agreement, including, without limitation, that your use is for |
| 11 | # the sole purpose of programming logic devices manufactured by |
| 12 | # Intel and sold by Intel or its authorized distributors. Please |
| 13 | # refer to the applicable agreement for further details, at |
| 14 | # https://fpgasoftware.intel.com/eula. |
| 15 | # Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition |
| 16 | # File: /home/lambda/Programs/intelQuartus/projects/vga/vga_io.csv |
| 17 | # Generated on: Sat Aug 26 14:34:23 2023 |
| 18 | # Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software. |
| 19 | To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation |
| 20 | B[7],Output,PIN_D12,8,B8_N0,PIN_AD1,,,,,, |
| 21 | B[6],Output,PIN_D11,8,B8_N1,PIN_AD2,,,,,, |
| 22 | B[5],Output,PIN_C12,8,B8_N0,PIN_B7,,,,,, |
| 23 | B[4],Output,PIN_A11,8,B8_N0,PIN_AC2,,,,,, |
| 24 | B[3],Output,PIN_B11,8,B8_N0,PIN_T8,,,,,, |
| 25 | B[2],Output,PIN_C11,8,B8_N1,PIN_U6,,,,,, |
| 26 | B[1],Output,PIN_A10,8,B8_N0,PIN_AD3,,,,,, |
| 27 | B[0],Output,PIN_B10,8,B8_N0,PIN_R3,,,,,, |
| 28 | G[7],Output,PIN_C9,8,B8_N1,PIN_AA3,,,,,, |
| 29 | G[6],Output,PIN_F10,8,B8_N1,PIN_D10,,,,,, |
| 30 | G[5],Output,PIN_B8,8,B8_N1,PIN_U4,,,,,, |
| 31 | G[4],Output,PIN_C8,8,B8_N1,PIN_U5,,,,,, |
| 32 | G[3],Output,PIN_H12,8,B8_N1,PIN_AC1,,,,,, |
| 33 | G[2],Output,PIN_F8,8,B8_N2,PIN_Y4,,,,,, |
| 34 | G[1],Output,PIN_G11,8,B8_N1,PIN_AB1,,,,,, |
| 35 | G[0],Output,PIN_G8,8,B8_N2,PIN_R6,,,,,, |
| 36 | HS,Output,PIN_G13,8,B8_N0,PIN_R5,,,,,, |
| 37 | px_clk,Input,,,,PIN_J1,,,,,, |
| 38 | R[7],Output,PIN_H10,8,B8_N1,PIN_Y3,,,,,, |
| 39 | R[6],Output,PIN_H8,8,B8_N2,PIN_U3,,,,,, |
| 40 | R[5],Output,PIN_J12,8,B8_N0,PIN_AC3,,,,,, |
| 41 | R[4],Output,PIN_G10,8,B8_N1,PIN_G23,,,,,, |
| 42 | R[3],Output,PIN_F12,8,B8_N1,PIN_AA4,,,,,, |
| 43 | R[2],Output,PIN_D10,8,B8_N1,PIN_AB2,,,,,, |
| 44 | R[1],Output,PIN_E11,8,B8_N1,PIN_W1,,,,,, |
| 45 | R[0],Output,PIN_E12,8,B8_N1,PIN_AB3,,,,,, |
| 46 | rst,Input,,,,PIN_Y2,,,,,, |
| 47 | VS,Output,PIN_C13,8,B8_N0,PIN_T3,,,,,, |