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99 lines
4.9 KiB
99 lines
4.9 KiB
# -------------------------------------------------------------------------- #
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#
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# Copyright (C) 2023 Intel Corporation. All rights reserved.
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# Your use of Intel Corporation's design tools, logic functions
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# and other software and tools, and any partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Intel Program License
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# Subscription Agreement, the Intel Quartus Prime License Agreement,
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# the Intel FPGA IP License Agreement, or other applicable license
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# agreement, including, without limitation, that your use is for
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# the sole purpose of programming logic devices manufactured by
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# Intel and sold by Intel or its authorized distributors. Please
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# refer to the applicable agreement for further details, at
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# https://fpgasoftware.intel.com/eula.
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#
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# -------------------------------------------------------------------------- #
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#
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# Quartus Prime
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# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
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# Date created = 13:50:20 August 26, 2023
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#
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# -------------------------------------------------------------------------- #
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#
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# Notes:
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#
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# 1) The default values for assignments are stored in the file:
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# vga_assignment_defaults.qdf
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# If this file doesn't exist, see file:
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# assignment_defaults.qdf
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#
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# 2) Intel recommends that you do not modify this file. This
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# file is updated automatically by the Quartus Prime software
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# and any changes you make may be lost or overwritten.
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#
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# -------------------------------------------------------------------------- #
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name DEVICE EP4CE115F29C7
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set_global_assignment -name TOP_LEVEL_ENTITY main
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:50:20 AUGUST 26, 2023"
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set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
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set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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set_location_assignment PIN_D12 -to B[7]
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set_location_assignment PIN_D11 -to B[6]
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set_location_assignment PIN_C12 -to B[5]
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set_location_assignment PIN_A11 -to B[4]
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set_location_assignment PIN_B11 -to B[3]
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set_location_assignment PIN_C11 -to B[2]
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set_location_assignment PIN_A10 -to B[1]
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set_location_assignment PIN_B10 -to B[0]
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set_location_assignment PIN_C9 -to G[7]
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set_location_assignment PIN_F10 -to G[6]
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set_location_assignment PIN_B8 -to G[5]
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set_location_assignment PIN_C8 -to G[4]
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set_location_assignment PIN_H12 -to G[3]
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set_location_assignment PIN_F8 -to G[2]
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set_location_assignment PIN_G11 -to G[1]
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set_location_assignment PIN_G8 -to G[0]
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set_location_assignment PIN_H10 -to R[7]
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set_location_assignment PIN_H8 -to R[6]
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set_location_assignment PIN_J12 -to R[5]
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set_location_assignment PIN_G10 -to R[4]
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set_location_assignment PIN_F12 -to R[3]
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set_location_assignment PIN_D10 -to R[2]
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set_location_assignment PIN_E11 -to R[1]
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set_location_assignment PIN_E12 -to R[0]
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set_location_assignment PIN_C13 -to VS
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set_location_assignment PIN_G13 -to HS
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set_location_assignment PIN_R24 -to rst
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
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set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
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set_global_assignment -name VHDL_FILE src/main.vhd
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set_global_assignment -name VHDL_FILE src/vga.vhd
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_location_assignment PIN_F11 -to VGA_BLANK
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set_location_assignment PIN_C10 -to VGA_SYNC
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set_global_assignment -name QIP_FILE pll.qip
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set_location_assignment PIN_AG14 -to clk
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set_location_assignment PIN_A12 -to VGA_CLK
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |