first commit

2023-08-27 08:41:55 +03:00 · 2023-08-27 08:41:55 +03:00 · 4a314484c6
commit 4a314484c6
16 changed files with 8125 additions and 0 deletions
--- a/#vga_io.csv#
+++ b/#vga_io.csv#
@ -0,0 +1,50 @@
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+
+# Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# File: /home/lambda/Programs/intelQuartus/projects/vga/vga_io.csv
+# Generated on: Sat Aug 26 14:20:03 2023
+
+# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
+
+To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
+B[7],Output,PIN_D12,8,B8_N0,PIN_AD1,,,,,,
+B[6],Output,,,,PIN_AD2,,,,,,
+B[5],Output,,,,PIN_B7,,,,,,
+B[4],Output,,,,PIN_AC2,,,,,,
+B[3],Output,,,,PIN_T8,,,,,,
+B[2],Output,,,,PIN_U6,,,,,,
+B[1],Output,,,,PIN_AD3,,,,,,
+B[0],Output,,,,PIN_R3,,,,,,
+G[7],Output,,,,PIN_AA3,,,,,,
+G[6],Output,,,,PIN_D10,,,,,,
+G[5],Output,,,,PIN_U4,,,,,,
+G[4],Output,,,,PIN_U5,,,,,,
+G[3],Output,,,,PIN_AC1,,,,,,
+G[2],Output,,,,PIN_Y4,,,,,,
+G[1],Output,,,,PIN_AB1,,,,,,
+G[0],Output,,,,PIN_R6,,,,,,
+HS,Output,,,,PIN_R5,,,,,,
+px_clk,Input,,,,PIN_J1,,,,,,
+R[7],Output,,,,PIN_Y3,,,,,,
+R[6],Output,,,,PIN_U3,,,,,,
+R[5],Output,,,,PIN_AC3,,,,,,
+R[4],Output,,,,PIN_G23,,,,,,
+R[3],Output,,,,PIN_AA4,,,,,,
+R[2],Output,,,,PIN_AB2,,,,,,
+R[1],Output,,,,PIN_W1,,,,,,
+R[0],Output,,,,PIN_AB3,,,,,,
+rst,Input,,,,PIN_Y2,,,,,,
+VS,Output,,,,PIN_T3,,,,,,
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1,70 @@
+# https://gist.github.com/nhasbun/71918796044b7ba89d6662133495f754
+# Working with Altera Quartus II (Q2) and do proper versioning is not that easy
+# but if you follow some rules it can be accomplished. :)
+# This file should be placed into the main directory where the .qpf file is
+# found. Generally Q2 throws all entities and so on in the main directory, but
+# you can place all stuff also in separate folders. This approach is followed
+# here. So when you create a new design create one or more folders where your
+# entities will be located and put a .gitignore in there that overrides the
+# ignores of this file, e.g. one single rule stating "!*" which allows now all
+# type of files. When you add a MegaFunction or another entity to your design,
+# simply add it to one of your private folders and Q2 will be happy and manage
+# everything quite good. When you want to do versioning of your generated
+# SOF/POF files, you can do this by redirecting the generated output to an own
+# folder. To do this go to:
+# "Assignments"
+# -> "Settings
+# -> "Compilation Process Settings"
+# -> "Save project output files in specified directory"
+# Now you can either place a .gitignore in the directory and allow the following
+# list of types:
+# !*.sof
+# !*.pof
+# or you create an own submodule in the folder to keep binary files out of your
+# design.
+
+# Need to keep all HDL files
+# *.vhd
+# *.v
+
+# ignore Quartus II generated files
+*_generation_script*
+*_inst.vhd
+*.bak
+*.cmp
+*.done
+*.eqn
+*.hex
+*.html
+*.jdi
+*.jpg
+# *.mif
+*.pin
+*.pof
+*.ptf.*
+*.qar
+*.qarlog
+*.qws
+*.rpt
+*.smsg
+*.sof
+*.sopc_builder
+*.summary
+*.tcl
+*.txt # Explicitly add any text files used
+*~
+*example*
+*sopc_*
+# *.sdc # I want those timing files
+
+# ignore Quartus II generated folders
+*/db/
+*/incremental_db/
+*/simulation/
+*/timing/
+*/testbench/
+*/*_sim/
+incremental_db/
+db/
+_output_files/
+PLLJ_PLLSPE_INFO.txt
--- a/output_files/vga.cdf
+++ b/output_files/vga.cdf
@ -0,0 +1,13 @@
+/* Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition */
+JedecChain;
+	FileRevision(JESD32A);
+	DefaultMfr(6E);
+
+	P ActionCode(Cfg)
+		Device PartName(EP4CE115F29) Path("/home/lambda/Programs/intelQuartus/projects/vga/output_files/") File("vga.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+	ChainType(JTAG);
+AlteraEnd;
--- a/output_files/vga.sld
+++ b/output_files/vga.sld
@ -0,0 +1 @@
+<sld_project_info/>
--- a/pll.ppf
+++ b/pll.ppf
@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+
+</global>
+</pinplan>
--- a/pll.qip
+++ b/pll.qip
@ -0,0 +1,7 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "22.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_inst.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
--- a/pll.vhd
+++ b/pll.vhd
@ -0,0 +1,351 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+-- ************************************************************
+
+
+--Copyright (C) 2023  Intel Corporation. All rights reserved.
+--Your use of Intel Corporation's design tools, logic functions 
+--and other software and tools, and any partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Intel Program License 
+--Subscription Agreement, the Intel Quartus Prime License Agreement,
+--the Intel FPGA IP License Agreement, or other applicable license
+--agreement, including, without limitation, that your use is for
+--the sole purpose of programming logic devices manufactured by
+--Intel and sold by Intel or its authorized distributors.  Please
+--refer to the applicable agreement for further details, at
+--https://fpgasoftware.intel.com/eula.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire4_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire4_bv(0 DOWNTO 0) <= "0";
+	sub_wire4    <= To_stdlogicvector(sub_wire4_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
+	sub_wire2    <= inclk0;
+	sub_wire3    <= sub_wire4(0 DOWNTO 0) & sub_wire2;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 2000,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 1007,
+		clk0_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone IV E",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_UNUSED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire3,
+		clk => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "25.174999"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "25.17500000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2000"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1007"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
--- a/simulation/modelsim/vga.sft
+++ b/simulation/modelsim/vga.sft
@ -0,0 +1 @@
+set tool_name "ModelSim (VHDL)"
--- a/simulation/modelsim/vga.vho
+++ b/simulation/modelsim/vga.vho
--- a/simulation/modelsim/vga_modelsim.xrf
+++ b/simulation/modelsim/vga_modelsim.xrf
@ -0,0 +1,391 @@
+vendor_name = ModelSim
+source_file = 1, /home/lambda/Programs/intelQuartus/projects/vga/src/main.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/projects/vga/src/vga.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/projects/vga/pll.qip
+source_file = 1, /home/lambda/Programs/intelQuartus/projects/vga/pll.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/vhdl/ieee/prmtvs_b.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/vhdl/ieee/prmtvs_p.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/vhdl/ieee/timing_b.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/vhdl/ieee/timing_p.vhd
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/altpll.tdf
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/aglobal221.inc
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/stratix_pll.inc
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/stratixii_pll.inc
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/cycloneii_pll.inc
+source_file = 1, /home/lambda/Programs/intelQuartus/quartus/libraries/megafunctions/cbx.lst
+source_file = 1, /home/lambda/Programs/intelQuartus/projects/vga/db/pll_altpll.v
+design_name = MAIN
+instance = comp, \VGA_BLANK~output\, VGA_BLANK~output, MAIN, 1
+instance = comp, \VGA_SYNC~output\, VGA_SYNC~output, MAIN, 1
+instance = comp, \VGA_CLK~output\, VGA_CLK~output, MAIN, 1
+instance = comp, \R[0]~output\, R[0]~output, MAIN, 1
+instance = comp, \R[1]~output\, R[1]~output, MAIN, 1
+instance = comp, \R[2]~output\, R[2]~output, MAIN, 1
+instance = comp, \R[3]~output\, R[3]~output, MAIN, 1
+instance = comp, \R[4]~output\, R[4]~output, MAIN, 1
+instance = comp, \R[5]~output\, R[5]~output, MAIN, 1
+instance = comp, \R[6]~output\, R[6]~output, MAIN, 1
+instance = comp, \R[7]~output\, R[7]~output, MAIN, 1
+instance = comp, \G[0]~output\, G[0]~output, MAIN, 1
+instance = comp, \G[1]~output\, G[1]~output, MAIN, 1
+instance = comp, \G[2]~output\, G[2]~output, MAIN, 1
+instance = comp, \G[3]~output\, G[3]~output, MAIN, 1
+instance = comp, \G[4]~output\, G[4]~output, MAIN, 1
+instance = comp, \G[5]~output\, G[5]~output, MAIN, 1
+instance = comp, \G[6]~output\, G[6]~output, MAIN, 1
+instance = comp, \G[7]~output\, G[7]~output, MAIN, 1
+instance = comp, \B[0]~output\, B[0]~output, MAIN, 1
+instance = comp, \B[1]~output\, B[1]~output, MAIN, 1
+instance = comp, \B[2]~output\, B[2]~output, MAIN, 1
+instance = comp, \B[3]~output\, B[3]~output, MAIN, 1
+instance = comp, \B[4]~output\, B[4]~output, MAIN, 1
+instance = comp, \B[5]~output\, B[5]~output, MAIN, 1
+instance = comp, \B[6]~output\, B[6]~output, MAIN, 1
+instance = comp, \B[7]~output\, B[7]~output, MAIN, 1
+instance = comp, \HS~output\, HS~output, MAIN, 1
+instance = comp, \VS~output\, VS~output, MAIN, 1
+instance = comp, \clk~input\, clk~input, MAIN, 1
+instance = comp, \myPLL|altpll_component|auto_generated|pll1\, myPLL|altpll_component|auto_generated|pll1, MAIN, 1
+instance = comp, \myPLL|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl\, myPLL|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl, MAIN, 1
+instance = comp, \myVGA|h_px_count[0]~10\, myVGA|h_px_count[0]~10, MAIN, 1
+instance = comp, \rst~input\, rst~input, MAIN, 1
+instance = comp, \myVGA|LessThan0~0\, myVGA|LessThan0~0, MAIN, 1
+instance = comp, \myVGA|LessThan0~1\, myVGA|LessThan0~1, MAIN, 1
+instance = comp, \myVGA|h_px_count[0]\, myVGA|h_px_count[0], MAIN, 1
+instance = comp, \myVGA|h_px_count[1]~12\, myVGA|h_px_count[1]~12, MAIN, 1
+instance = comp, \myVGA|h_px_count[1]\, myVGA|h_px_count[1], MAIN, 1
+instance = comp, \myVGA|h_px_count[2]~14\, myVGA|h_px_count[2]~14, MAIN, 1
+instance = comp, \myVGA|h_px_count[2]\, myVGA|h_px_count[2], MAIN, 1
+instance = comp, \myVGA|h_px_count[3]~16\, myVGA|h_px_count[3]~16, MAIN, 1
+instance = comp, \myVGA|h_px_count[3]\, myVGA|h_px_count[3], MAIN, 1
+instance = comp, \myVGA|h_px_count[4]~18\, myVGA|h_px_count[4]~18, MAIN, 1
+instance = comp, \myVGA|h_px_count[4]\, myVGA|h_px_count[4], MAIN, 1
+instance = comp, \myVGA|h_px_count[5]~20\, myVGA|h_px_count[5]~20, MAIN, 1
+instance = comp, \myVGA|h_px_count[5]\, myVGA|h_px_count[5], MAIN, 1
+instance = comp, \myVGA|h_px_count[6]~22\, myVGA|h_px_count[6]~22, MAIN, 1
+instance = comp, \myVGA|h_px_count[6]\, myVGA|h_px_count[6], MAIN, 1
+instance = comp, \myVGA|h_px_count[7]~24\, myVGA|h_px_count[7]~24, MAIN, 1
+instance = comp, \myVGA|h_px_count[7]\, myVGA|h_px_count[7], MAIN, 1
+instance = comp, \myVGA|h_px_count[8]~26\, myVGA|h_px_count[8]~26, MAIN, 1
+instance = comp, \myVGA|h_px_count[8]\, myVGA|h_px_count[8], MAIN, 1
+instance = comp, \myVGA|h_px_count[9]~28\, myVGA|h_px_count[9]~28, MAIN, 1
+instance = comp, \myVGA|h_px_count[9]\, myVGA|h_px_count[9], MAIN, 1
+instance = comp, \myVGA|ball_bounce:ball_speed_x[1]~0\, myVGA|\ball_bounce:ball_speed_x[1]~0, MAIN, 1
+instance = comp, \myVGA|Add1~0\, myVGA|Add1~0, MAIN, 1
+instance = comp, \myVGA|v_px_count[9]~0\, myVGA|v_px_count[9]~0, MAIN, 1
+instance = comp, \myVGA|v_px_count[0]\, myVGA|v_px_count[0], MAIN, 1
+instance = comp, \myVGA|Add1~2\, myVGA|Add1~2, MAIN, 1
+instance = comp, \myVGA|Add1~4\, myVGA|Add1~4, MAIN, 1
+instance = comp, \myVGA|v_px_count[2]~3\, myVGA|v_px_count[2]~3, MAIN, 1
+instance = comp, \myVGA|v_px_count[2]\, myVGA|v_px_count[2], MAIN, 1
+instance = comp, \myVGA|Add1~6\, myVGA|Add1~6, MAIN, 1
+instance = comp, \myVGA|v_px_count[3]~4\, myVGA|v_px_count[3]~4, MAIN, 1
+instance = comp, \myVGA|v_px_count[3]\, myVGA|v_px_count[3], MAIN, 1
+instance = comp, \myVGA|Add1~8\, myVGA|Add1~8, MAIN, 1
+instance = comp, \myVGA|v_px_count[4]\, myVGA|v_px_count[4], MAIN, 1
+instance = comp, \myVGA|Add1~10\, myVGA|Add1~10, MAIN, 1
+instance = comp, \myVGA|v_px_count[5]\, myVGA|v_px_count[5], MAIN, 1
+instance = comp, \myVGA|Add1~12\, myVGA|Add1~12, MAIN, 1
+instance = comp, \myVGA|v_px_count[6]\, myVGA|v_px_count[6], MAIN, 1
+instance = comp, \myVGA|Add1~14\, myVGA|Add1~14, MAIN, 1
+instance = comp, \myVGA|v_px_count[7]\, myVGA|v_px_count[7], MAIN, 1
+instance = comp, \myVGA|Add1~16\, myVGA|Add1~16, MAIN, 1
+instance = comp, \myVGA|v_px_count[8]\, myVGA|v_px_count[8], MAIN, 1
+instance = comp, \myVGA|Add1~18\, myVGA|Add1~18, MAIN, 1
+instance = comp, \myVGA|v_px_count[9]~2\, myVGA|v_px_count[9]~2, MAIN, 1
+instance = comp, \myVGA|v_px_count[9]\, myVGA|v_px_count[9], MAIN, 1
+instance = comp, \myVGA|Equal0~1\, myVGA|Equal0~1, MAIN, 1
+instance = comp, \myVGA|Equal0~0\, myVGA|Equal0~0, MAIN, 1
+instance = comp, \myVGA|Equal0~2\, myVGA|Equal0~2, MAIN, 1
+instance = comp, \myVGA|v_px_count[1]~1\, myVGA|v_px_count[1]~1, MAIN, 1
+instance = comp, \myVGA|v_px_count[1]~5\, myVGA|v_px_count[1]~5, MAIN, 1
+instance = comp, \myVGA|v_px_count[1]\, myVGA|v_px_count[1], MAIN, 1
+instance = comp, \myVGA|Equal1~0\, myVGA|Equal1~0, MAIN, 1
+instance = comp, \myVGA|Equal1~1\, myVGA|Equal1~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[0]~1\, myVGA|\ball_bounce:count[0]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[0]\, myVGA|\ball_bounce:count[0], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[1]~1\, myVGA|\ball_bounce:count[1]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[1]\, myVGA|\ball_bounce:count[1], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[2]~1\, myVGA|\ball_bounce:count[2]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[2]\, myVGA|\ball_bounce:count[2], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[3]~1\, myVGA|\ball_bounce:count[3]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[3]\, myVGA|\ball_bounce:count[3], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[4]~1\, myVGA|\ball_bounce:count[4]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[4]\, myVGA|\ball_bounce:count[4], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[5]~1\, myVGA|\ball_bounce:count[5]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[5]\, myVGA|\ball_bounce:count[5], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[6]~1\, myVGA|\ball_bounce:count[6]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[6]\, myVGA|\ball_bounce:count[6], MAIN, 1
+instance = comp, \myVGA|LessThan7~0\, myVGA|LessThan7~0, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[7]~1\, myVGA|\ball_bounce:count[7]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[7]\, myVGA|\ball_bounce:count[7], MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[8]~1\, myVGA|\ball_bounce:count[8]~1, MAIN, 1
+instance = comp, \myVGA|ball_bounce:count[8]\, myVGA|\ball_bounce:count[8], MAIN, 1
+instance = comp, \myVGA|LessThan7~1\, myVGA|LessThan7~1, MAIN, 1
+instance = comp, \myVGA|ball_b[0]~7\, myVGA|ball_b[0]~7, MAIN, 1
+instance = comp, \myVGA|ball_bounce:ball_speed_x[1]\, myVGA|\ball_bounce:ball_speed_x[1], MAIN, 1
+instance = comp, \myVGA|ball_b[0]~24\, myVGA|ball_b[0]~24, MAIN, 1
+instance = comp, \myVGA|ball_b[0]\, myVGA|ball_b[0], MAIN, 1
+instance = comp, \myVGA|ball_x[1]~10\, myVGA|ball_x[1]~10, MAIN, 1
+instance = comp, \myVGA|ball_x[1]~11\, myVGA|ball_x[1]~11, MAIN, 1
+instance = comp, \myVGA|ball_x[1]\, myVGA|ball_x[1], MAIN, 1
+instance = comp, \myVGA|ball_x[2]~13\, myVGA|ball_x[2]~13, MAIN, 1
+instance = comp, \myVGA|ball_x[2]\, myVGA|ball_x[2], MAIN, 1
+instance = comp, \myVGA|ball_x[3]~15\, myVGA|ball_x[3]~15, MAIN, 1
+instance = comp, \myVGA|ball_x[3]\, myVGA|ball_x[3], MAIN, 1
+instance = comp, \myVGA|ball_x[4]~17\, myVGA|ball_x[4]~17, MAIN, 1
+instance = comp, \myVGA|ball_x[4]\, myVGA|ball_x[4], MAIN, 1
+instance = comp, \myVGA|ball_x[5]~19\, myVGA|ball_x[5]~19, MAIN, 1
+instance = comp, \myVGA|ball_x[5]\, myVGA|ball_x[5], MAIN, 1
+instance = comp, \myVGA|Add19~0\, myVGA|Add19~0, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[9]\, myVGA|\vary_ball_width:count[9], MAIN, 1
+instance = comp, \myVGA|Add18~0\, myVGA|Add18~0, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[0]\, myVGA|\vary_ball_width:count[0], MAIN, 1
+instance = comp, \myVGA|Add18~2\, myVGA|Add18~2, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[1]\, myVGA|\vary_ball_width:count[1], MAIN, 1
+instance = comp, \myVGA|Add18~4\, myVGA|Add18~4, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[2]\, myVGA|\vary_ball_width:count[2], MAIN, 1
+instance = comp, \myVGA|Add18~6\, myVGA|Add18~6, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[3]\, myVGA|\vary_ball_width:count[3], MAIN, 1
+instance = comp, \myVGA|Add18~8\, myVGA|Add18~8, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[4]\, myVGA|\vary_ball_width:count[4], MAIN, 1
+instance = comp, \myVGA|Add18~10\, myVGA|Add18~10, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[5]\, myVGA|\vary_ball_width:count[5], MAIN, 1
+instance = comp, \myVGA|Add18~12\, myVGA|Add18~12, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[6]\, myVGA|\vary_ball_width:count[6], MAIN, 1
+instance = comp, \myVGA|Add18~14\, myVGA|Add18~14, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[7]\, myVGA|\vary_ball_width:count[7], MAIN, 1
+instance = comp, \myVGA|Add18~16\, myVGA|Add18~16, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:count[8]\, myVGA|\vary_ball_width:count[8], MAIN, 1
+instance = comp, \myVGA|Add18~18\, myVGA|Add18~18, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[5]~2\, myVGA|BALL_WIDTH[5]~2, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[5]~1\, myVGA|BALL_WIDTH[5]~1, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[5]~0\, myVGA|BALL_WIDTH[5]~0, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[5]~3\, myVGA|BALL_WIDTH[5]~3, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[0]\, myVGA|BALL_WIDTH[0], MAIN, 1
+instance = comp, \myVGA|Add19~2\, myVGA|Add19~2, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[1]~5\, myVGA|BALL_WIDTH[1]~5, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[1]\, myVGA|BALL_WIDTH[1], MAIN, 1
+instance = comp, \myVGA|Add19~4\, myVGA|Add19~4, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[2]\, myVGA|BALL_WIDTH[2], MAIN, 1
+instance = comp, \myVGA|growth~0\, myVGA|growth~0, MAIN, 1
+instance = comp, \myVGA|vary_ball_width:growth[1]\, myVGA|\vary_ball_width:growth[1], MAIN, 1
+instance = comp, \myVGA|Add19~6\, myVGA|Add19~6, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[3]~4\, myVGA|BALL_WIDTH[3]~4, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[3]\, myVGA|BALL_WIDTH[3], MAIN, 1
+instance = comp, \myVGA|Add19~8\, myVGA|Add19~8, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[4]\, myVGA|BALL_WIDTH[4], MAIN, 1
+instance = comp, \myVGA|growth~1\, myVGA|growth~1, MAIN, 1
+instance = comp, \myVGA|growth~2\, myVGA|growth~2, MAIN, 1
+instance = comp, \myVGA|Add19~10\, myVGA|Add19~10, MAIN, 1
+instance = comp, \myVGA|BALL_WIDTH[5]\, myVGA|BALL_WIDTH[5], MAIN, 1
+instance = comp, \myVGA|LessThan10~1\, myVGA|LessThan10~1, MAIN, 1
+instance = comp, \myVGA|LessThan10~3\, myVGA|LessThan10~3, MAIN, 1
+instance = comp, \myVGA|LessThan10~5\, myVGA|LessThan10~5, MAIN, 1
+instance = comp, \myVGA|LessThan10~7\, myVGA|LessThan10~7, MAIN, 1
+instance = comp, \myVGA|LessThan10~9\, myVGA|LessThan10~9, MAIN, 1
+instance = comp, \myVGA|LessThan10~10\, myVGA|LessThan10~10, MAIN, 1
+instance = comp, \myVGA|ball_x[6]~21\, myVGA|ball_x[6]~21, MAIN, 1
+instance = comp, \myVGA|ball_x[6]\, myVGA|ball_x[6], MAIN, 1
+instance = comp, \myVGA|ball_x[7]~23\, myVGA|ball_x[7]~23, MAIN, 1
+instance = comp, \myVGA|ball_x[7]\, myVGA|ball_x[7], MAIN, 1
+instance = comp, \myVGA|LessThan10~12\, myVGA|LessThan10~12, MAIN, 1
+instance = comp, \myVGA|Add3~0\, myVGA|Add3~0, MAIN, 1
+instance = comp, \myVGA|Add3~2\, myVGA|Add3~2, MAIN, 1
+instance = comp, \myVGA|Add3~4\, myVGA|Add3~4, MAIN, 1
+instance = comp, \myVGA|Add3~6\, myVGA|Add3~6, MAIN, 1
+instance = comp, \myVGA|Add3~8\, myVGA|Add3~8, MAIN, 1
+instance = comp, \myVGA|LessThan8~6\, myVGA|LessThan8~6, MAIN, 1
+instance = comp, \myVGA|Add3~10\, myVGA|Add3~10, MAIN, 1
+instance = comp, \myVGA|LessThan8~7\, myVGA|LessThan8~7, MAIN, 1
+instance = comp, \myVGA|ball_x[8]~25\, myVGA|ball_x[8]~25, MAIN, 1
+instance = comp, \myVGA|ball_x[8]\, myVGA|ball_x[8], MAIN, 1
+instance = comp, \myVGA|LessThan8~0\, myVGA|LessThan8~0, MAIN, 1
+instance = comp, \myVGA|LessThan8~1\, myVGA|LessThan8~1, MAIN, 1
+instance = comp, \myVGA|LessThan8~2\, myVGA|LessThan8~2, MAIN, 1
+instance = comp, \myVGA|LessThan8~3\, myVGA|LessThan8~3, MAIN, 1
+instance = comp, \myVGA|LessThan8~4\, myVGA|LessThan8~4, MAIN, 1
+instance = comp, \myVGA|LessThan8~5\, myVGA|LessThan8~5, MAIN, 1
+instance = comp, \myVGA|LessThan8~8\, myVGA|LessThan8~8, MAIN, 1
+instance = comp, \myVGA|ball_speed_x~0\, myVGA|ball_speed_x~0, MAIN, 1
+instance = comp, \myVGA|ball_x[9]~27\, myVGA|ball_x[9]~27, MAIN, 1
+instance = comp, \myVGA|ball_x[9]\, myVGA|ball_x[9], MAIN, 1
+instance = comp, \myVGA|Add14~0\, myVGA|Add14~0, MAIN, 1
+instance = comp, \myVGA|Add14~2\, myVGA|Add14~2, MAIN, 1
+instance = comp, \myVGA|Add14~4\, myVGA|Add14~4, MAIN, 1
+instance = comp, \myVGA|Add14~6\, myVGA|Add14~6, MAIN, 1
+instance = comp, \myVGA|Add14~8\, myVGA|Add14~8, MAIN, 1
+instance = comp, \myVGA|Add14~10\, myVGA|Add14~10, MAIN, 1
+instance = comp, \myVGA|Add14~12\, myVGA|Add14~12, MAIN, 1
+instance = comp, \myVGA|Add14~14\, myVGA|Add14~14, MAIN, 1
+instance = comp, \myVGA|Add14~16\, myVGA|Add14~16, MAIN, 1
+instance = comp, \myVGA|Add14~18\, myVGA|Add14~18, MAIN, 1
+instance = comp, \myVGA|LessThan12~1\, myVGA|LessThan12~1, MAIN, 1
+instance = comp, \myVGA|LessThan12~3\, myVGA|LessThan12~3, MAIN, 1
+instance = comp, \myVGA|LessThan12~5\, myVGA|LessThan12~5, MAIN, 1
+instance = comp, \myVGA|LessThan12~7\, myVGA|LessThan12~7, MAIN, 1
+instance = comp, \myVGA|LessThan12~9\, myVGA|LessThan12~9, MAIN, 1
+instance = comp, \myVGA|LessThan12~11\, myVGA|LessThan12~11, MAIN, 1
+instance = comp, \myVGA|LessThan12~13\, myVGA|LessThan12~13, MAIN, 1
+instance = comp, \myVGA|LessThan12~15\, myVGA|LessThan12~15, MAIN, 1
+instance = comp, \myVGA|LessThan12~17\, myVGA|LessThan12~17, MAIN, 1
+instance = comp, \myVGA|LessThan12~18\, myVGA|LessThan12~18, MAIN, 1
+instance = comp, \myVGA|ball_y[1]~9\, myVGA|ball_y[1]~9, MAIN, 1
+instance = comp, \myVGA|ball_y[1]~10\, myVGA|ball_y[1]~10, MAIN, 1
+instance = comp, \myVGA|ball_y[1]\, myVGA|ball_y[1], MAIN, 1
+instance = comp, \myVGA|ball_y[2]~12\, myVGA|ball_y[2]~12, MAIN, 1
+instance = comp, \myVGA|ball_y[2]\, myVGA|ball_y[2], MAIN, 1
+instance = comp, \myVGA|ball_y[3]~14\, myVGA|ball_y[3]~14, MAIN, 1
+instance = comp, \myVGA|ball_y[3]\, myVGA|ball_y[3], MAIN, 1
+instance = comp, \myVGA|ball_y[4]~16\, myVGA|ball_y[4]~16, MAIN, 1
+instance = comp, \myVGA|ball_y[4]\, myVGA|ball_y[4], MAIN, 1
+instance = comp, \myVGA|ball_y[5]~18\, myVGA|ball_y[5]~18, MAIN, 1
+instance = comp, \myVGA|ball_y[5]\, myVGA|ball_y[5], MAIN, 1
+instance = comp, \myVGA|ball_y[6]~20\, myVGA|ball_y[6]~20, MAIN, 1
+instance = comp, \myVGA|ball_y[6]\, myVGA|ball_y[6], MAIN, 1
+instance = comp, \myVGA|LessThan11~1\, myVGA|LessThan11~1, MAIN, 1
+instance = comp, \myVGA|LessThan11~3\, myVGA|LessThan11~3, MAIN, 1
+instance = comp, \myVGA|LessThan11~5\, myVGA|LessThan11~5, MAIN, 1
+instance = comp, \myVGA|LessThan11~7\, myVGA|LessThan11~7, MAIN, 1
+instance = comp, \myVGA|LessThan11~9\, myVGA|LessThan11~9, MAIN, 1
+instance = comp, \myVGA|LessThan11~10\, myVGA|LessThan11~10, MAIN, 1
+instance = comp, \myVGA|Add5~0\, myVGA|Add5~0, MAIN, 1
+instance = comp, \myVGA|Add5~2\, myVGA|Add5~2, MAIN, 1
+instance = comp, \myVGA|Add5~4\, myVGA|Add5~4, MAIN, 1
+instance = comp, \myVGA|Add5~6\, myVGA|Add5~6, MAIN, 1
+instance = comp, \myVGA|Add5~8\, myVGA|Add5~8, MAIN, 1
+instance = comp, \myVGA|Add5~10\, myVGA|Add5~10, MAIN, 1
+instance = comp, \myVGA|LessThan9~1\, myVGA|LessThan9~1, MAIN, 1
+instance = comp, \myVGA|LessThan9~3\, myVGA|LessThan9~3, MAIN, 1
+instance = comp, \myVGA|LessThan9~5\, myVGA|LessThan9~5, MAIN, 1
+instance = comp, \myVGA|LessThan9~7\, myVGA|LessThan9~7, MAIN, 1
+instance = comp, \myVGA|LessThan9~9\, myVGA|LessThan9~9, MAIN, 1
+instance = comp, \myVGA|LessThan9~11\, myVGA|LessThan9~11, MAIN, 1
+instance = comp, \myVGA|LessThan9~12\, myVGA|LessThan9~12, MAIN, 1
+instance = comp, \myVGA|ball_speed_y~0\, myVGA|ball_speed_y~0, MAIN, 1
+instance = comp, \myVGA|ball_bounce:ball_speed_y[1]~0\, myVGA|\ball_bounce:ball_speed_y[1]~0, MAIN, 1
+instance = comp, \myVGA|ball_bounce:ball_speed_y[1]\, myVGA|\ball_bounce:ball_speed_y[1], MAIN, 1
+instance = comp, \myVGA|ball_y[7]~22\, myVGA|ball_y[7]~22, MAIN, 1
+instance = comp, \myVGA|ball_y[7]\, myVGA|ball_y[7], MAIN, 1
+instance = comp, \myVGA|ball_speed_y~1\, myVGA|ball_speed_y~1, MAIN, 1
+instance = comp, \myVGA|ball_y[8]~24\, myVGA|ball_y[8]~24, MAIN, 1
+instance = comp, \myVGA|ball_y[8]\, myVGA|ball_y[8], MAIN, 1
+instance = comp, \myVGA|Add16~0\, myVGA|Add16~0, MAIN, 1
+instance = comp, \myVGA|Add16~2\, myVGA|Add16~2, MAIN, 1
+instance = comp, \myVGA|Add16~4\, myVGA|Add16~4, MAIN, 1
+instance = comp, \myVGA|Add16~6\, myVGA|Add16~6, MAIN, 1
+instance = comp, \myVGA|Add16~8\, myVGA|Add16~8, MAIN, 1
+instance = comp, \myVGA|Add16~10\, myVGA|Add16~10, MAIN, 1
+instance = comp, \myVGA|Add16~12\, myVGA|Add16~12, MAIN, 1
+instance = comp, \myVGA|Add16~14\, myVGA|Add16~14, MAIN, 1
+instance = comp, \myVGA|Add16~16\, myVGA|Add16~16, MAIN, 1
+instance = comp, \myVGA|Add16~18\, myVGA|Add16~18, MAIN, 1
+instance = comp, \myVGA|LessThan14~1\, myVGA|LessThan14~1, MAIN, 1
+instance = comp, \myVGA|LessThan14~3\, myVGA|LessThan14~3, MAIN, 1
+instance = comp, \myVGA|LessThan14~5\, myVGA|LessThan14~5, MAIN, 1
+instance = comp, \myVGA|LessThan14~7\, myVGA|LessThan14~7, MAIN, 1
+instance = comp, \myVGA|LessThan14~9\, myVGA|LessThan14~9, MAIN, 1
+instance = comp, \myVGA|LessThan14~11\, myVGA|LessThan14~11, MAIN, 1
+instance = comp, \myVGA|LessThan14~13\, myVGA|LessThan14~13, MAIN, 1
+instance = comp, \myVGA|LessThan14~15\, myVGA|LessThan14~15, MAIN, 1
+instance = comp, \myVGA|LessThan14~17\, myVGA|LessThan14~17, MAIN, 1
+instance = comp, \myVGA|LessThan14~18\, myVGA|LessThan14~18, MAIN, 1
+instance = comp, \myVGA|Add14~20\, myVGA|Add14~20, MAIN, 1
+instance = comp, \myVGA|Add15~0\, myVGA|Add15~0, MAIN, 1
+instance = comp, \myVGA|Add15~2\, myVGA|Add15~2, MAIN, 1
+instance = comp, \myVGA|Add15~4\, myVGA|Add15~4, MAIN, 1
+instance = comp, \myVGA|Add15~6\, myVGA|Add15~6, MAIN, 1
+instance = comp, \myVGA|Add15~8\, myVGA|Add15~8, MAIN, 1
+instance = comp, \myVGA|Add15~10\, myVGA|Add15~10, MAIN, 1
+instance = comp, \myVGA|Add15~12\, myVGA|Add15~12, MAIN, 1
+instance = comp, \myVGA|Add15~14\, myVGA|Add15~14, MAIN, 1
+instance = comp, \myVGA|Add15~16\, myVGA|Add15~16, MAIN, 1
+instance = comp, \myVGA|Add15~18\, myVGA|Add15~18, MAIN, 1
+instance = comp, \myVGA|LessThan13~1\, myVGA|LessThan13~1, MAIN, 1
+instance = comp, \myVGA|LessThan13~3\, myVGA|LessThan13~3, MAIN, 1
+instance = comp, \myVGA|LessThan13~5\, myVGA|LessThan13~5, MAIN, 1
+instance = comp, \myVGA|LessThan13~7\, myVGA|LessThan13~7, MAIN, 1
+instance = comp, \myVGA|LessThan13~9\, myVGA|LessThan13~9, MAIN, 1
+instance = comp, \myVGA|LessThan13~11\, myVGA|LessThan13~11, MAIN, 1
+instance = comp, \myVGA|LessThan13~13\, myVGA|LessThan13~13, MAIN, 1
+instance = comp, \myVGA|LessThan13~15\, myVGA|LessThan13~15, MAIN, 1
+instance = comp, \myVGA|LessThan13~17\, myVGA|LessThan13~17, MAIN, 1
+instance = comp, \myVGA|LessThan13~18\, myVGA|LessThan13~18, MAIN, 1
+instance = comp, \myVGA|Add17~0\, myVGA|Add17~0, MAIN, 1
+instance = comp, \myVGA|Add17~2\, myVGA|Add17~2, MAIN, 1
+instance = comp, \myVGA|Add17~4\, myVGA|Add17~4, MAIN, 1
+instance = comp, \myVGA|Add17~6\, myVGA|Add17~6, MAIN, 1
+instance = comp, \myVGA|Add17~8\, myVGA|Add17~8, MAIN, 1
+instance = comp, \myVGA|Add17~10\, myVGA|Add17~10, MAIN, 1
+instance = comp, \myVGA|Add17~12\, myVGA|Add17~12, MAIN, 1
+instance = comp, \myVGA|Add17~14\, myVGA|Add17~14, MAIN, 1
+instance = comp, \myVGA|Add17~16\, myVGA|Add17~16, MAIN, 1
+instance = comp, \myVGA|Add17~18\, myVGA|Add17~18, MAIN, 1
+instance = comp, \myVGA|LessThan15~1\, myVGA|LessThan15~1, MAIN, 1
+instance = comp, \myVGA|LessThan15~3\, myVGA|LessThan15~3, MAIN, 1
+instance = comp, \myVGA|LessThan15~5\, myVGA|LessThan15~5, MAIN, 1
+instance = comp, \myVGA|LessThan15~7\, myVGA|LessThan15~7, MAIN, 1
+instance = comp, \myVGA|LessThan15~9\, myVGA|LessThan15~9, MAIN, 1
+instance = comp, \myVGA|LessThan15~11\, myVGA|LessThan15~11, MAIN, 1
+instance = comp, \myVGA|LessThan15~13\, myVGA|LessThan15~13, MAIN, 1
+instance = comp, \myVGA|LessThan15~15\, myVGA|LessThan15~15, MAIN, 1
+instance = comp, \myVGA|LessThan15~17\, myVGA|LessThan15~17, MAIN, 1
+instance = comp, \myVGA|LessThan15~18\, myVGA|LessThan15~18, MAIN, 1
+instance = comp, \myVGA|Add15~20\, myVGA|Add15~20, MAIN, 1
+instance = comp, \myVGA|ball_draw~0\, myVGA|ball_draw~0, MAIN, 1
+instance = comp, \myVGA|ball_draw~1\, myVGA|ball_draw~1, MAIN, 1
+instance = comp, \myVGA|color_mask[0]\, myVGA|color_mask[0], MAIN, 1
+instance = comp, \myVGA|can_draw~0\, myVGA|can_draw~0, MAIN, 1
+instance = comp, \myVGA|V_SYNC_GEN~0\, myVGA|V_SYNC_GEN~0, MAIN, 1
+instance = comp, \myVGA|can_draw~1\, myVGA|can_draw~1, MAIN, 1
+instance = comp, \myVGA|can_draw\, myVGA|can_draw, MAIN, 1
+instance = comp, \myVGA|R[1]~0\, myVGA|R[1]~0, MAIN, 1
+instance = comp, \myVGA|ball_g[1]~7\, myVGA|ball_g[1]~7, MAIN, 1
+instance = comp, \myVGA|ball_g[1]\, myVGA|ball_g[1], MAIN, 1
+instance = comp, \myVGA|R[2]~1\, myVGA|R[2]~1, MAIN, 1
+instance = comp, \myVGA|ball_g[2]~9\, myVGA|ball_g[2]~9, MAIN, 1
+instance = comp, \myVGA|ball_g[2]\, myVGA|ball_g[2], MAIN, 1
+instance = comp, \myVGA|R[3]~2\, myVGA|R[3]~2, MAIN, 1
+instance = comp, \myVGA|ball_g[3]~11\, myVGA|ball_g[3]~11, MAIN, 1
+instance = comp, \myVGA|ball_g[3]\, myVGA|ball_g[3], MAIN, 1
+instance = comp, \myVGA|R[4]~3\, myVGA|R[4]~3, MAIN, 1
+instance = comp, \myVGA|ball_g[4]~13\, myVGA|ball_g[4]~13, MAIN, 1
+instance = comp, \myVGA|ball_g[4]\, myVGA|ball_g[4], MAIN, 1
+instance = comp, \myVGA|R[5]~4\, myVGA|R[5]~4, MAIN, 1
+instance = comp, \myVGA|ball_g[5]~15\, myVGA|ball_g[5]~15, MAIN, 1
+instance = comp, \myVGA|ball_g[5]\, myVGA|ball_g[5], MAIN, 1
+instance = comp, \myVGA|R[6]~5\, myVGA|R[6]~5, MAIN, 1
+instance = comp, \myVGA|ball_g[6]~17\, myVGA|ball_g[6]~17, MAIN, 1
+instance = comp, \myVGA|ball_g[6]\, myVGA|ball_g[6], MAIN, 1
+instance = comp, \myVGA|R[7]~6\, myVGA|R[7]~6, MAIN, 1
+instance = comp, \myVGA|ball_g[7]~19\, myVGA|ball_g[7]~19, MAIN, 1
+instance = comp, \myVGA|ball_g[7]\, myVGA|ball_g[7], MAIN, 1
+instance = comp, \myVGA|G[7]~0\, myVGA|G[7]~0, MAIN, 1
+instance = comp, \myVGA|ball_b[1]~9\, myVGA|ball_b[1]~9, MAIN, 1
+instance = comp, \myVGA|ball_b[1]~10\, myVGA|ball_b[1]~10, MAIN, 1
+instance = comp, \myVGA|ball_b[1]\, myVGA|ball_b[1], MAIN, 1
+instance = comp, \myVGA|B[1]~0\, myVGA|B[1]~0, MAIN, 1
+instance = comp, \myVGA|ball_b[2]~12\, myVGA|ball_b[2]~12, MAIN, 1
+instance = comp, \myVGA|ball_b[2]\, myVGA|ball_b[2], MAIN, 1
+instance = comp, \myVGA|B[2]~1\, myVGA|B[2]~1, MAIN, 1
+instance = comp, \myVGA|ball_b[3]~14\, myVGA|ball_b[3]~14, MAIN, 1
+instance = comp, \myVGA|ball_b[3]\, myVGA|ball_b[3], MAIN, 1
+instance = comp, \myVGA|B[3]~2\, myVGA|B[3]~2, MAIN, 1
+instance = comp, \myVGA|ball_b[4]~16\, myVGA|ball_b[4]~16, MAIN, 1
+instance = comp, \myVGA|ball_b[4]\, myVGA|ball_b[4], MAIN, 1
+instance = comp, \myVGA|B[4]~3\, myVGA|B[4]~3, MAIN, 1
+instance = comp, \myVGA|ball_b[5]~18\, myVGA|ball_b[5]~18, MAIN, 1
+instance = comp, \myVGA|ball_b[5]\, myVGA|ball_b[5], MAIN, 1
+instance = comp, \myVGA|B[5]~4\, myVGA|B[5]~4, MAIN, 1
+instance = comp, \myVGA|ball_b[6]~20\, myVGA|ball_b[6]~20, MAIN, 1
+instance = comp, \myVGA|ball_b[6]\, myVGA|ball_b[6], MAIN, 1
+instance = comp, \myVGA|B[6]~5\, myVGA|B[6]~5, MAIN, 1
+instance = comp, \myVGA|ball_b[7]~22\, myVGA|ball_b[7]~22, MAIN, 1
+instance = comp, \myVGA|ball_b[7]\, myVGA|ball_b[7], MAIN, 1
+instance = comp, \myVGA|B[7]~6\, myVGA|B[7]~6, MAIN, 1
+instance = comp, \myVGA|H_SYNC_GEN~0\, myVGA|H_SYNC_GEN~0, MAIN, 1
+instance = comp, \myVGA|H_SYNC_GEN~1\, myVGA|H_SYNC_GEN~1, MAIN, 1
+instance = comp, \myVGA|HS\, myVGA|HS, MAIN, 1
+instance = comp, \myVGA|V_SYNC_GEN~1\, myVGA|V_SYNC_GEN~1, MAIN, 1
+instance = comp, \myVGA|V_SYNC_GEN~2\, myVGA|V_SYNC_GEN~2, MAIN, 1
+instance = comp, \myVGA|VS\, myVGA|VS, MAIN, 1
--- a/src/greybox_tmp/cbx_args.txt
+++ b/src/greybox_tmp/cbx_args.txt
@ -0,0 +1,58 @@
+BANDWIDTH_TYPE=AUTO
+CLK0_DIVIDE_BY=2000
+CLK0_DUTY_CYCLE=50
+CLK0_MULTIPLY_BY=1007
+CLK0_PHASE_SHIFT=0
+COMPENSATE_CLOCK=CLK0
+INCLK0_INPUT_FREQUENCY=20000
+INTENDED_DEVICE_FAMILY="Cyclone IV E"
+LPM_TYPE=altpll
+OPERATION_MODE=NORMAL
+PLL_TYPE=AUTO
+PORT_ACTIVECLOCK=PORT_UNUSED
+PORT_ARESET=PORT_UNUSED
+PORT_CLKBAD0=PORT_UNUSED
+PORT_CLKBAD1=PORT_UNUSED
+PORT_CLKLOSS=PORT_UNUSED
+PORT_CLKSWITCH=PORT_UNUSED
+PORT_CONFIGUPDATE=PORT_UNUSED
+PORT_FBIN=PORT_UNUSED
+PORT_INCLK0=PORT_USED
+PORT_INCLK1=PORT_UNUSED
+PORT_LOCKED=PORT_UNUSED
+PORT_PFDENA=PORT_UNUSED
+PORT_PHASECOUNTERSELECT=PORT_UNUSED
+PORT_PHASEDONE=PORT_UNUSED
+PORT_PHASESTEP=PORT_UNUSED
+PORT_PHASEUPDOWN=PORT_UNUSED
+PORT_PLLENA=PORT_UNUSED
+PORT_SCANACLR=PORT_UNUSED
+PORT_SCANCLK=PORT_UNUSED
+PORT_SCANCLKENA=PORT_UNUSED
+PORT_SCANDATA=PORT_UNUSED
+PORT_SCANDATAOUT=PORT_UNUSED
+PORT_SCANDONE=PORT_UNUSED
+PORT_SCANREAD=PORT_UNUSED
+PORT_SCANWRITE=PORT_UNUSED
+PORT_clk0=PORT_USED
+PORT_clk1=PORT_UNUSED
+PORT_clk2=PORT_UNUSED
+PORT_clk3=PORT_UNUSED
+PORT_clk4=PORT_UNUSED
+PORT_clk5=PORT_UNUSED
+PORT_clkena0=PORT_UNUSED
+PORT_clkena1=PORT_UNUSED
+PORT_clkena2=PORT_UNUSED
+PORT_clkena3=PORT_UNUSED
+PORT_clkena4=PORT_UNUSED
+PORT_clkena5=PORT_UNUSED
+PORT_extclk0=PORT_UNUSED
+PORT_extclk1=PORT_UNUSED
+PORT_extclk2=PORT_UNUSED
+PORT_extclk3=PORT_UNUSED
+WIDTH_CLOCK=5
+DEVICE_FAMILY="Cyclone IV E"
+CBX_AUTO_BLACKBOX=ALL
+inclk
+inclk
+clk
--- a/src/main.vhd
+++ b/src/main.vhd
@ -0,0 +1,52 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity MAIN is
+
+  port (
+    VGA_BLANK, VGA_SYNC, VGA_CLK : out std_logic;
+    clk, rst                     : in  std_logic;
+    R, G, B                      : out std_logic_vector (7 downto 0);
+    HS, VS                       : out std_logic);
+
+end entity MAIN;
+
+
+architecture mymain of MAIN is
+  component VGA is
+    port(
+      px_clk, rst : in  std_logic;
+      R, G, B     : out std_logic_vector (7 downto 0);
+      HS, VS      : out std_logic);
+  end component VGA;
+
+  component PLL is
+    port (
+      inclk0 : in  std_logic := '0';
+      c0     : out std_logic
+      );
+  end component PLL;
+
+  signal px_clk : std_logic;
+
+begin
+
+  --  USED BY the ADC
+  VGA_BLANK <= '1';
+  VGA_SYNC  <= '0';
+  VGA_CLK   <= px_clk;
+
+  myVGA : VGA port map (
+    px_clk => px_clk,                   -- this signals a new px
+    rst    => rst,
+    R      => R,
+    G      => G,
+    B      => B,
+    HS     => HS,
+    VS     => VS);                      -- this signals a new frame
+
+  myPLL : PLL port map (
+    inclk0 => clk,
+    c0     => px_clk);
+
+end architecture;
--- a/src/vga.vhd
+++ b/src/vga.vhd
@ -0,0 +1,183 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity VGA is
+
+  port (
+    px_clk, rst : in  std_logic;
+    R, G, B     : out std_logic_vector (7 downto 0);
+    HS, VS      : out std_logic);
+
+end entity VGA;
+
+architecture myVGA of VGA is
+
+  -- Horizontal timings
+  constant H_VISIBLE_AREA : integer := 640;
+  constant H_FP           : integer := 16;
+  constant H_SYNC         : integer := 96;
+  constant H_BP           : integer := 48;
+  constant H_ALL          : integer := 800;
+
+  -- Vertical timings
+  constant V_VISIBLE_AREA : integer := 480;
+  constant V_FP           : integer := 10;
+  constant V_SYNC         : integer := 2;
+  constant V_BP           : integer := 33;
+  constant V_ALL          : integer := 525;
+
+  -- local
+  signal h_px_count : integer range 0 to H_ALL;
+  signal v_px_count : integer range 0 to V_ALL;
+  signal can_draw   : std_logic;
+
+  -- ball
+  signal ball_x     : integer range 0 to H_VISIBLE_AREA;
+  signal ball_y     : integer range 0 to V_VISIBLE_AREA;
+  signal color_mask : std_logic_vector (7 downto 0);
+  signal BALL_WIDTH : integer range 10 to 50;
+  signal ball_r     : integer range 0 to 255;  -- colors
+  signal ball_g     : integer range 0 to 255;
+  signal ball_b     : integer range 0 to 255;
+
+begin  -- architecture myVGA
+
+  VH_PX_COUNTER : process (px_clk, rst) is
+  begin  -- process H_PX_COUNTER
+    if rst = '0' then                   -- asynchronous reset (active low)
+      h_px_count <= 0;
+    elsif rising_edge(px_clk) then      -- rising clock edge
+      if h_px_count < H_ALL then
+        h_px_count <= h_px_count + 1;
+      else
+        h_px_count <= 0;
+        v_px_count <= v_px_count + 1;
+      end if;
+      if v_px_count = V_ALL then
+        v_px_count <= 0;
+      end if;
+    end if;
+  end process VH_PX_COUNTER;
+
+  V_SYNC_GEN : process (px_clk, rst, v_px_count) is
+  begin  -- process V_SYNC_GEN
+    if rst = '0' then                   -- asynchronous reset (active low)
+      VS <= '1';
+    elsif rising_edge(px_clk) then      -- rising clock edge
+      if v_px_count >= V_VISIBLE_AREA + V_FP and v_px_count < V_ALL - V_BP then
+        VS <= '0';
+      else
+        VS <= '1';
+      end if;
+    end if;
+  end process V_SYNC_GEN;
+
+  H_SYNC_GEN : process (px_clk, rst, h_px_count) is
+  begin  -- process H_SYNC_GEN
+    if rst = '0' then                   -- asynchronous reset (active low)
+      HS <= '1';
+    elsif rising_edge(px_clk) then      -- rising clock edge
+      if h_px_count >= H_VISIBLE_AREA + H_FP and h_px_count < H_ALL - H_BP then
+        HS <= '0';
+      else
+        HS <= '1';
+      end if;
+    end if;
+  end process H_SYNC_GEN;
+
+  CAN_DRAW_GEN : process (px_clk, rst, v_px_count, h_px_count) is
+  begin  -- process CAN_DRAW_GEN
+    if rst = '0' then                   -- asynchronous reset (active low)
+
+    elsif rising_edge(px_clk) then      -- rising clock edge
+      if v_px_count < V_VISIBLE_AREA and h_px_count < H_VISIBLE_AREA then
+        can_draw <= '1';
+      else
+        can_draw <= '0';
+      end if;
+    end if;
+  end process CAN_DRAW_GEN;
+
+  process (can_draw) is
+  begin  -- process
+    if can_draw = '1' then
+      R <= color_mask and std_logic_vector(to_unsigned(ball_r, 8));
+      G <= color_mask and std_logic_vector(to_unsigned(ball_g, 8));
+      B <= color_mask and std_logic_vector(to_unsigned(ball_b, 8));
+    else
+      R <= "00000000";
+      G <= "00000000";
+      B <= "00000000";
+    end if;
+  end process;
+
+  ball_bounce : process (v_px_count) is
+    variable count        : integer range 0 to 300;
+    variable ball_speed_x : integer range -1 to 1 := 1;
+    variable ball_speed_y : integer range -1 to 1 := 1;
+  begin  -- process ball_bounce
+    if rising_edge(px_clk) and v_px_count = 0 then
+
+      if count < 300 then
+        count := count + 1;
+      else
+        count := 0;
+
+        if ball_x >= H_VISIBLE_AREA - BALL_WIDTH then
+          ball_speed_x := - ball_speed_x;
+        end if;
+        if ball_y >= V_VISIBLE_AREA - BALL_WIDTH then
+          ball_speed_y := - ball_speed_y;
+        end if;
+
+        if ball_x < BALL_WIDTH then
+          ball_x       <= BALL_WIDTH + 1;
+          ball_speed_x := abs(ball_speed_x);
+        end if;
+        if ball_y < BALL_WIDTH then
+          ball_y       <= BALL_WIDTH + 1;
+          ball_speed_y := abs(ball_speed_y);
+        end if;
+
+        ball_x <= ball_x + ball_speed_x;
+        ball_y <= ball_y + ball_speed_y;
+
+        -- random colors
+        ball_r <= ball_r + 2;
+        ball_g <= ball_g + 1;
+        ball_b <= ball_b + 3;
+      end if;
+
+    end if;
+  end process ball_bounce;
+
+  ball_draw : process (px_clk) is
+  begin  -- process ball_draw
+    if rising_edge(px_clk) then
+      if h_px_count < ball_x + BALL_WIDTH and h_px_count >= ball_x - BALL_WIDTH and
+        v_px_count < ball_y + BALL_WIDTH and v_px_count >= ball_y - BALL_WIDTH then
+        color_mask <= "11111111";
+      else
+        color_mask <= "00000000";
+      end if;
+    end if;
+  end process ball_draw;
+
+  vary_ball_width : process (v_px_count) is
+    variable count  : integer range 0 to 1023;
+    variable growth : integer range -1 to 1 := 1;
+  begin  -- process ball_bounce
+    if rising_edge(px_clk) and v_px_count = 0 then
+      count := count + 1;
+      if count = 1023 then
+        if BALL_WIDTH = 50 then
+          growth := -1;
+        elsif BALL_WIDTH = 10 then
+          growth := 1;
+        end if;
+        BALL_WIDTH <= BALL_WIDTH + growth;
+      end if;
+    end if;
+  end process;
+end architecture myVGA;
--- a/vga.qpf
+++ b/vga.qpf
@ -0,0 +1,31 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# Date created = 13:50:20  August 26, 2023
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "22.1"
+DATE = "13:50:20  August 26, 2023"
+
+# Revisions
+
+PROJECT_REVISION = "vga"
--- a/vga.qsf
+++ b/vga.qsf
@ -0,0 +1,99 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus Prime
+# Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# Date created = 13:50:20  August 26, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		vga_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Intel recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus Prime software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE115F29C7
+set_global_assignment -name TOP_LEVEL_ENTITY main
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 22.1STD.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:50:20  AUGUST 26, 2023"
+set_global_assignment -name LAST_QUARTUS_VERSION "22.1std.2 Lite Edition"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
+set_location_assignment PIN_D12 -to B[7]
+set_location_assignment PIN_D11 -to B[6]
+set_location_assignment PIN_C12 -to B[5]
+set_location_assignment PIN_A11 -to B[4]
+set_location_assignment PIN_B11 -to B[3]
+set_location_assignment PIN_C11 -to B[2]
+set_location_assignment PIN_A10 -to B[1]
+set_location_assignment PIN_B10 -to B[0]
+set_location_assignment PIN_C9 -to G[7]
+set_location_assignment PIN_F10 -to G[6]
+set_location_assignment PIN_B8 -to G[5]
+set_location_assignment PIN_C8 -to G[4]
+set_location_assignment PIN_H12 -to G[3]
+set_location_assignment PIN_F8 -to G[2]
+set_location_assignment PIN_G11 -to G[1]
+set_location_assignment PIN_G8 -to G[0]
+set_location_assignment PIN_H10 -to R[7]
+set_location_assignment PIN_H8 -to R[6]
+set_location_assignment PIN_J12 -to R[5]
+set_location_assignment PIN_G10 -to R[4]
+set_location_assignment PIN_F12 -to R[3]
+set_location_assignment PIN_D10 -to R[2]
+set_location_assignment PIN_E11 -to R[1]
+set_location_assignment PIN_E12 -to R[0]
+set_location_assignment PIN_C13 -to VS
+set_location_assignment PIN_G13 -to HS
+set_location_assignment PIN_R24 -to rst
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name VHDL_FILE src/main.vhd
+set_global_assignment -name VHDL_FILE src/vga.vhd
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_location_assignment PIN_F11 -to VGA_BLANK
+set_location_assignment PIN_C10 -to VGA_SYNC
+set_global_assignment -name QIP_FILE pll.qip
+set_location_assignment PIN_AG14 -to clk
+set_location_assignment PIN_A12 -to VGA_CLK
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--- a/vga_io.csv
+++ b/vga_io.csv
@ -0,0 +1,50 @@
+# Copyright (C) 2023  Intel Corporation. All rights reserved.
+# Your use of Intel Corporation's design tools, logic functions 
+# and other software and tools, and any partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Intel Program License 
+# Subscription Agreement, the Intel Quartus Prime License Agreement,
+# the Intel FPGA IP License Agreement, or other applicable license
+# agreement, including, without limitation, that your use is for
+# the sole purpose of programming logic devices manufactured by
+# Intel and sold by Intel or its authorized distributors.  Please
+# refer to the applicable agreement for further details, at
+# https://fpgasoftware.intel.com/eula.
+
+# Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
+# File: /home/lambda/Programs/intelQuartus/projects/vga/vga_io.csv
+# Generated on: Sat Aug 26 14:34:23 2023
+
+# Note: The column header names should not be changed if you wish to import this .csv file into the Quartus Prime software.
+
+To,Direction,Location,I/O Bank,VREF Group,Fitter Location,I/O Standard,Reserved,Current Strength,Slew Rate,Differential Pair,Strict Preservation
+B[7],Output,PIN_D12,8,B8_N0,PIN_AD1,,,,,,
+B[6],Output,PIN_D11,8,B8_N1,PIN_AD2,,,,,,
+B[5],Output,PIN_C12,8,B8_N0,PIN_B7,,,,,,
+B[4],Output,PIN_A11,8,B8_N0,PIN_AC2,,,,,,
+B[3],Output,PIN_B11,8,B8_N0,PIN_T8,,,,,,
+B[2],Output,PIN_C11,8,B8_N1,PIN_U6,,,,,,
+B[1],Output,PIN_A10,8,B8_N0,PIN_AD3,,,,,,
+B[0],Output,PIN_B10,8,B8_N0,PIN_R3,,,,,,
+G[7],Output,PIN_C9,8,B8_N1,PIN_AA3,,,,,,
+G[6],Output,PIN_F10,8,B8_N1,PIN_D10,,,,,,
+G[5],Output,PIN_B8,8,B8_N1,PIN_U4,,,,,,
+G[4],Output,PIN_C8,8,B8_N1,PIN_U5,,,,,,
+G[3],Output,PIN_H12,8,B8_N1,PIN_AC1,,,,,,
+G[2],Output,PIN_F8,8,B8_N2,PIN_Y4,,,,,,
+G[1],Output,PIN_G11,8,B8_N1,PIN_AB1,,,,,,
+G[0],Output,PIN_G8,8,B8_N2,PIN_R6,,,,,,
+HS,Output,PIN_G13,8,B8_N0,PIN_R5,,,,,,
+px_clk,Input,,,,PIN_J1,,,,,,
+R[7],Output,PIN_H10,8,B8_N1,PIN_Y3,,,,,,
+R[6],Output,PIN_H8,8,B8_N2,PIN_U3,,,,,,
+R[5],Output,PIN_J12,8,B8_N0,PIN_AC3,,,,,,
+R[4],Output,PIN_G10,8,B8_N1,PIN_G23,,,,,,
+R[3],Output,PIN_F12,8,B8_N1,PIN_AA4,,,,,,
+R[2],Output,PIN_D10,8,B8_N1,PIN_AB2,,,,,,
+R[1],Output,PIN_E11,8,B8_N1,PIN_W1,,,,,,
+R[0],Output,PIN_E12,8,B8_N1,PIN_AB3,,,,,,
+rst,Input,,,,PIN_Y2,,,,,,
+VS,Output,PIN_C13,8,B8_N0,PIN_T3,,,,,,